The silicon bipolar transistor has been the device of choice for motor drive circuits, appliance controls, robotics and lighting ballasts. This is because bipolar transistors can be designed to handle relatively large current densities in the range of 40-50 A/cm.sup.2 and support relatively high blocking voltages in the range of 500-1000 V.
Despite the attractive power ratings achieved by bipolar transistors, there exist several fundamental drawbacks to their suitability for all high power applications. First of all, bipolar transistors are current controlled devices which require relatively large base currents, typically one fifth to one tenth of the collector current, to maintain the transistor in an operating mode. Proportionally larger base currents can be expected for applications which also require high speed turn-off. Because of the large base current demands, the base drive circuitry for controlling turn-on and turn-off is relatively complex and expensive. Bipolar transistors are also vulnerable to premature breakdown if a high current and high voltage are simultaneously applied to the device, as commonly required in inductive power circuit applications. Furthermore, it is relatively difficult to operate bipolar transistors in parallel because current diversion to a single transistor typically occurs at high temperatures, making emitter ballasting schemes necessary.
The silicon power MOSFET was developed to address this base drive problem. In a power MOSFET, the gate is used to provide turn-on and turn-off control upon the application of an appropriate gate signal bias. For example, turn-on in an N-type enhancement MOSFET occurs when a conductive N-type inversion layer is formed in the P-type channel region in response to the application of a positive gate bias. The inversion layer electrically connects the N-type source and drain regions and allows for majority carrier conduction therebetween. The power MOSFET's gate electrode is separated from the channel region by an intervening insulating layer, typically silicon dioxide. Because the gate is insulated from the channel region, little if any gate current is required to maintain the MOSFET in a conductive state or to switch the MOSFET from an on-state to an off-state or vice-versa. The gate current is kept small during switching because the gate forms a capacitor with the MOSFET's channel region. Thus, only charging and discharging current ("displacement current") is required during switching. Because of the high input impedance associated with the insulated-gate electrode, minimal current demands are placed on the gate and the gate drive circuitry can be easily implemented.
Moreover, because current conduction in the MOSFET occurs through majority carrier transport only, the delay associated with the recombination of excess minority carriers is not present. Accordingly, the switching speed of power MOSFETs can be made orders of magnitude faster than that of bipolar transistors. Unlike bipolar transistors, power MOSFETs can be designed to withstand high current densities and the application of high voltages for relatively long durations, without encountering the destructive failure mechanism known as "second breakdown". Power MOSFETs can also easily be paralleled, because the forward voltage drop of power MOSFETs increases with increasing temperature, thereby promoting an even current distribution in parallel connected devices.
In view of the above desirable characteristics, many variations of power MOSFETs have been designed for high power applications. Two of the most popular types are the double-diffused MOSFET (DMOS) device and the trench-gate MOSFET (UMOS). Both of these devices are vertical devices, having a source region located on one face of a semiconductor substrate and a drain region located on an opposite face.
The DMOS structure and its operation and fabrication are described in the textbook entitled Modern Power Devices by inventor B.J. Baliga, the disclosure of which is hereby incorporated herein by reference. Chapter 6 of this textbook describes power MOSFETs at pages 263-343. FIG. 1 herein is a reproduction of FIG. 6.1(a) from the above cited textbook, and illustrates a cross-sectional view of a basic DMOS structure. As shown, the DMOS structure is fabricated using planar diffusion technology, with a refractory gate such as polycrystalline silicon (polysilicon). The P-base region and the N+ source region are typically diffused through a common window defined by the edge of the polysilicon gate. The P-base region is typically driven in deeper than the N+ source. The difference in the lateral diffusion between the P-base and N+ source regions defines the channel length. The length of the channel is an important design parameter because it has a strong influence on the DMOSFET's on-resistance and transconductance.
Turn-on of a power DMOS is controlled by the insulated-gate electrode. Referring to FIG. 1, a highly conductive inversion layer channel can be generated in the P-base region upon the application of a positive gate bias. This inversion layer channel electrically connects the source region to the drift region, thereby allowing conduction between the source and drain upon the application of an appropriate drain bias. To switch the power DMOS to the off-state, the gate bias voltage is reduced to zero by externally short circuiting the gate electrode to the source electrode. In order to insure that the parasitic bipolar transistor formed by the N+ source, P-base and N-drift region is kept inactive during operation of the power DMOS, the P-base region is short circuited to the N+ source, as shown in FIG. 1.
The UMOS device, also referred to as a "Trench DMOS" device, is described in publications entitled An Ultra-Low On-Resistance Power MOSFET Fabricated by Using a Fully Self-Aligned Process, by Ueda et al., IEEE Transactions on Electron Devices, Vol. ED34, No. 4, April, (1987), pp. 926-930; Numerical and Experimental Comparison of 60 V Vertical Double-Diffused MOSFETS and MOSFETS with a Trench-Gate Structure by Chang, Solid State Electronics, Vol. 32, No. 3, pp. 247-251, (1989); Trench DMOS Transistor Technology for High-Current (100A Range) Switching by Buluce et al., Solid State Electronics, Vol. 34, No. 5, pp. 493-507, (1991); Extended Trench-Gate Power UMOSFET Structure with Ultralow Specific On-Resistance by Syau et al., Electronics Letters, Vol. 28, No. 9, pp. 865-867, (1992); and Optimized Trench MOSFET Technologies for Power Devices by Shenai, IEEE Transactions on Electron Devices, Vol. 39, No. 6, pp. 1435-1443, June (1992). As described in the aforementioned article by Ueda, the UMOS contains a rectangular trench which makes each unit cell relatively small and provides for high levels of integration. FIG. 2 herein is a reproduction of a portion of FIG. 1 from the Ueda article. The device is fabricated by diffusing P-base and N+ source regions into an N- epitaxial drift region of an N+ substrate. Reactive ion etching is then used to form rectangular grooves or trenches in the substrate, followed by an oxidation step to form the gate insulating layer. A first polysilicon layer is also grown and slightly oxidized and a second polysilicon layer is deposited for groove filling. In order to form the gate, the first polysilicon layer is etched off and then the device is metallized.
However, for high power applications, the performance of both the vertical DMOS and UMOS structures is limited by the presence of a P-N junction between the source and drain, which can slow the response time when switching from a high forward current on-state to the off-state. A silicon power MOSFET which does not suffer from the presence of a P-N junction is shown in FIG. 3. FIG. 3 is a reproduction of FIG. 4 from U.S Pat. No. 4,903,189 to Ngo et al., entitled Low Noise, High Frequency Synchronous Rectifier, the disclosure of which is hereby incorporated herein by reference. This MOSFET 170, which includes trenches 178 at a face thereof is commonly referred to as an accumulation-mode FET ("ACCU-FET") because turn-on is achieved by forming a conductive accumulation layer between the FET's source 186 and drain 182 regions.
In addition to the above-mentioned silicon-based power transistors, attempts have been made to develop power transistors based in silicon carbide because of silicon carbide's wide bandgap, high melting point, low dielectric constant, high breakdown field strength, high thermal conductivity and high saturated electron drift velocity compared to silicon. These characteristics allow silicon carbide power devices to operate at higher temperatures, higher power levels and with lower specific on-resistance than conventional silicon based power devices. One attempt to take advantage of silicon carbide's preferred characteristics is disclosed in commonly assigned U.S. Pat. No. 5,233,215 to inventor B.J. Baliga, entitled Silicon Carbide Power MOSFET with Floating Field Ring and Floating Field Plate, the disclosure of which is hereby incorporated herein by reference. FIG. 4 is a reproduction of FIG. 4 from the Baliga '215 patent. Unfortunately, operation of this device requires the formation of an N-type silicon carbide inversion layer channel in region 18, which may causes a relatively high channel resistance and high on-state resistance. It may also be difficult to form good quality oxides on P-type silicon carbide using conventional oxidation techniques.
Another attempt to develop silicon carbide devices for high power applications is disclosed in an article by Kelner et al. entitled .beta.-SiC MESFET's and Buried-Gate JFET's, IEEE Electron Device Letters, Vol. EDL-8, No. 9, pp. 428-430, September (1987). Kelner et al. discloses a lateral silicon carbide MESFET having an N-type active region on top of a P-type layer and a schottky barrier gate. Kelner et al. also discloses a JFET having a buried-gate electrode formed of the P-type layer. Unfortunately, the Kelner et al. FETs suffer from an unnecessarily high output conductance, caused by leakage current in the P-type layer. Furthermore, complete channel pinch-off between the source and drain regions could not be attained.
Therefore, notwithstanding the recognized benefits of using power FETs for applications requiring high-speed turn-off and low gate-drive currents, there continues to be a need for power devices which are capable of sustaining high currents at high temperatures with relatively low on-state resistance. There also continues to be a need for power devices which are capable of blocking relatively large drain to source voltages and which do not suffer from large leakage currents.